The present invention relates generally to a very low power “System on a Chip” (SOC) which can operate intermittently, but which most of the time is in its sleep mode or standby mode, and which can be powered for a very long amount of time (e.g., more than about a year) by a very small “button” battery. More particularly, the present invention relates to circuitry for reducing the amount of the MOS transistor gate leakage currents which typically contribute to power consumption of circuitry in a “switchable power domain” of the SOC chip.
The term “domain” or “power domain” generally refers to SOC chips. In a SOC chip, a certain activity or type of circuitry is provided in a region referred to as an “island” of a substrate on which the SOC chip is fabricated. One or more such power domains on the substrate may be coupled to a particular power supply voltage VDD by means of a one or more switches that are controlled by a control signal. Such power domains are referred to as “switchable power domains”. One or more power domains of an SOC chip may be non-switchable or “always on” power domains (hereinafter, “AON power domains”) that are always connected to VDD.
FIG. 1 shows a switchable power domain circuit 1 including a conventional CMOS inverter 3 coupled to ground and also coupled by a power switch 4 to power supply voltage VDD. CMOS inverter 3 includes a N-channel transistor MN1 having its source connected to ground, its body (or bulk) electrode connected to ground, its gate connected to an input conductor 2, and its drain connected to the drain of a P-channel MOS transistor MP1. The gate of transistor MP1 is connected to conductor 2, which conducts an input logic signal VLOGIC-IN. The source and body electrodes of transistor MP1 are connected to one terminal of power switch 4. The other terminal of power switch 4 is connected to VDD. A control terminal 15 of power switch 4 receives a control signal SWITCH_CONTROL. Arrow 5N designates the direction of the current path of a gate leakage current ILEAKN of N-channel transistor MN1, and arrow 5P designates the direction of the current path of a gate leakage current ILEAKP of P-channel transistor MP1. The gate leakage currents ILEAKN and ILEAKP “tunnel” across the gate oxides of N-channel transistor MN1 and P-channel transistor MN1, respectively, if the voltage between the gate electrode and the body electrode (i.e., the voltage across the gate oxide) is sufficiently high. Such gate leakage currents typically have magnitudes in the range of picoamperes for HVT (high threshold voltage) transistors and in the range of microamperes for SVT (standard threshold voltage) transistors, as a cumulative effect of all of the transistors in a corresponding power domain of a SOC chip.
The gate leakage current ILEAKN in FIG. 1 is always present when power switch 4 is closed and VLOGIC-IN is simultaneously at a high “1” voltage level. For example, if VDD is equal to 1.25 V (volts) and power switch 4 is closed, then ILEAKN for an SVT transistor may be approximately 70 pA (picoamperes), and if power switch 4 is open, then ILEAKN may be much higher, approximately 800 pA. Also, if power switch 4 is open, and VLOGIC-IN is at a high “1” level, there may be a significant level of gate leakage current ILEAKP flowing through P-channel transistor MP1 if the source of transistor MP1 has “floated” down to a voltage level near ground. If a typical CMOS inverter 3 used in one embodiment of the invention, the total gate leakage current is zero pA for values of the input voltage between zero and approximately 700 mV (millivolts) and increases exponentially to nearly 200 pA when the CMOS inverter input voltage reaches about 1.1 V, and increases to about 400 pA when the input voltage reaches about 1.2 V, and increases to about 800 pA when the input voltage reaches about 1.25 V.
FIGS. 2A through 2D show several different examples of circuit configurations that can cause unacceptably high gate leakage currents that may be unacceptable in a CMOS SOC chip which needs to operate from a button battery for a long period of time (e.g., for longer than a year). FIG. 2A shows a switchable power domain 10A in an SOC chip which also includes an AON (always on) power domain 8A. AON power domain 8A includes various AON logic circuitry 11 and ISO control circuitry 12, both of which are directly connected to VDD and both of which also receive input signals from various other circuitry (not shown) on the chip. Switchable power domain 10A typically includes buffer circuitry 3 (which may be a CMOS inverter), switchable logic circuitry 16, and an isolation circuit or cell 14, all of which receive their operating power directly from VDD through conductor 6 and power switch 4 whenever power switch 4 is closed by an “active” logic level of a switch control signal SWITCH_CONTROL on conductor 15. Note that the signal ISO can open but cannot close power switch 4. Conductor 6 is connected to one terminal of power switch 4, the other terminal of which is connected to VDD. Power switch 4 is opened in response to the active level of isolation control signal ISO and is closed the rest of the time. The output of AON logic circuitry 11 is connected to the input of input buffer circuitry (or CMOS inverter) 3 in switchable power domain 10A. The output of input buffer circuitry 3 is connected by conductor 7 to the input of switchable logic circuitry 16. The output of switchable logic circuitry 16 is connected to one input of isolation cell 14. An enable input of isolation cell 14 is connected by conductor 17 to the output ISO of AON isolation signal control circuitry 12. To turn switchable power domain 10A OFF, first an active level of ISO on conductor 17 domain is asserted. Then switch control input signal SWITCH_CONTROL on conductor 15 de-asserted. To turn switchable power domain 10A on, first switch control signal SWITCH_CONTROL is asserted, and then signal ISO on conductor 17 signal de-asserted.
When the switchable power domain 10A is OFF, power switch 4 is open but the input(s) of one or more switchable power domains may continue to receive input signals that may be either logic “1”s or logic “0”s from AON logic circuitry 11. Consequently, the CMOS input inverter 3 in FIG. 1, which can be used as input buffer circuitry 3 in FIG. 2, is likely to have a significant amount of gate leakage current, depending on whether it is receiving a logic “1” or a logic “0” from AON logic circuitry 11. (Conductor 7 will be, in a sense, “floating” but since switchable power domain 10A is OFF it will not cause any “floating” CMOS gate leakage current. The only leakage current that occurs in this case is the gate leakage current in buffer 3.)
Referring to FIG. 2B, a D-type flip-flop circuit 18 is shown which typically performs the function of retaining data in a switchable power domain if that switchable power domain is in its OFF condition. D-type flip-flop circuit 18 includes an input inverter X2, a master latch 18A including CMOS input inverters X3 and X4, a CMOS transmission gate M1, a slave latch 18B including CMOS output inverters X5 and X6, and an output inverter X7. The output of master latch 18A is coupled by CMOS transmission gate M1 to the input of slave latch 18B. D-type flip-flop 18 is composed of HVT transistors and master latch 18A includes only SVT transistors, in order to reduce gate leakage currents therein, except that output inverter X7 is formed using SVT (standard threshold VT) transistors to provide increased drive current at the output of output inverter X7 so it can adequately drive other circuitry (not shown). Note that since the output of slave latch 18B may be generating a “1” voltage level while its associated switchable power domain is OFF, the gate of output inverter X7 may have an a high gate leakage current (see FIG. 1) that may be as high as roughly 1.5 μA, as a cumulative effect of all of the transistors on a SOC chip. (The term “low threshold transistor” or “SVT transistor” is used herein to refer to relatively small, relatively inexpensive CMOS transistors of the kind used for most of the transistors on a SOC chip, whereas the term “high threshold transistor” or “HVT transistor” is used herein to refer to relatively large, relatively expensive CMOS transistors of having a substantially higher threshold voltage VT than that of the SVT transistors.)
Referring to FIG. 2C, circuitry 20 includes a memory array 20-1 which is composed of HVT transistors to reduce gate leakage currents therein while a switchable power domain containing memory array 20-1 is in its OFF condition, i.e., during the “retention mode” of memory array 20-1. The individual memory cells in memory array 20-1 can be similar to or the same as the D-type flip-flops 18 of FIG. 2C. Circuitry 20 in FIG. 2C also includes conventional associated peripheral logic circuitry 20-2 coupled to memory array 20-1 to effectuate ordinary read and write operations of memory array 20-1. Peripheral logic 20-2 is contained in a switchable power domain. It is conventional to improve the read/write performance achieved by means of peripheral logic circuitry 20-2 by utilizing SVT transistors. Unfortunately, this greatly increases the amount of gate leakage current of the kind previously described with reference to FIG. 1 and substantially decreases the life of a button battery used to power circuitry 20 of FIG. 2C.
Referring next to FIG. 2D, a low-power SOC chip 21 includes a switchable power domain 21-1 which is illustrated as being in its OFF condition. Switchable power domain 21-1 includes logic circuitry 21-2, an input of which is driven by AON (always on) circuitry 21-3 in an adjacent AON power domain. AON circuitry 21-3 may include digital and/or analog circuitry that may be applying a high logic “1” voltage level to digital logic circuitry 21-2 in switchable power domain 21-1. Consequently, there may be unacceptably large amounts of gate leakage current in logic circuitry 21-2 even while power domain 21-1 is in its OFF condition.
Referring next to FIG. 2E, a typical prior art isolation cell circuit 14 (also mentioned in FIG. 2A) includes a CMOS inverter including a P-channel transistor M02 and a N-channel transistor M03 having their corresponding gate electrodes connected to an input signal INPUT on conductor 23-1. The source of transistor M03 is connected to ground and its drain is connected to the drain of transistor M02 and to the gate electrodes of another CMOS inverter including P-channel transistor M06 and N-channel transistor M04. The source of transistor M02 is connected by conductor 6A to the source of transistor M06 and to the drain of a P-channel power switch transistor M01. The source of transistor M04 is connected to ground and its drain is connected to the drain of transistor M06 and to an output conductor 23-2 on which the signal OUTPUT is generated. The source of transistor M01 is connected to VDD and its gate is connected by conductor 17 to AON isolation control circuitry 12 (shown in FIG. 2A) to receive isolation control signal ISO. A N-channel transistor M05 has its gate electrode connected to ISO, its source connected to ground, and its drain connected to conductor 23-2. If ISO is at its “active” level, transistor M01 of ISO cell 14 may be OFF, but the gate electrodes of transistors M02 and M06 may be electrically floating. However, this will not cause indeterminate output voltage levels on conductor 23-2 because when ISO is low, transistor M05 will be ON, which will ensure a “0” voltage level on conductor 23-2.
A problem of prior art ISO cell circuit 14 circuit in FIG. 2E is that the ISO signal generated on conductor 17 by the AON ISO control circuitry 12 (see FIG. 2A) causes gate leakage current at the gate of transistor M01. Also, using HVT transistors in isolation cell 14 substantially reduces the operating speed of the SOC chip in which isolation cell 14 is located. Furthermore, using SVT transistors in the output inverter X7 of a D-type flip-flop (as shown in FIG. 2B) can cause substantially increased gate leakage current in N-channel transistor M05.
Thus, it should be appreciated that during the sleep mode or standby mode of an SOC, the switched power domains containing high-performance logic circuitry have been switched OFF to substantially reduce gate leakage currents therein. However, if AON circuitry is applying a “1” voltage level to the gate electrode of a SVT transistor in a switchable power domain that is in its OFF condition, there nevertheless will be a substantial amount of gate leakage current in that transistor even though its power domain is OFF.
It also should be appreciated that some low-power RF products including a SOC chip need to be powered for more than a year by a small button-type battery. In many such products the SOC chip spends more than 90% of its time in its sleep or standby mode. Therefore, the amount of gate leakage current and associated power dissipation in the SOC chip during sleep or standby mode operation is very important to the objective of extending the life of the battery. Unfortunately, the above described conventional technique of using high threshold voltage isolation cells composed of HVT transistors in isolation cells to reduce gate leakage current reduces circuit performance in various ways.
Therefore, there is an unmet need for an improved circuit and method for reducing the amount of gate leakage current in a power domain that is switched OFF in an integrated circuit chip.
There also is an unmet need for an improved circuit and method for extending the life of a battery that needs to provide power as needed to a SOC chip for a long period of time.